Anindya S. Dhar: search on Z-Library

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1

FPGA realization of a CORDIC based FFT processor for biomedical signal processing

Ayan Banerjee, Anindya Sundar Dhar, Swapna Banerjee

Journal:

Microprocessors and Microsystems

Year:

2001

Language:

english

File:

PDF, 500 KB

english, 2001

2

CORDIC-based Hann windowed sliding DFT architecture for real-time spectrum analysis with bounded error-accumulation

Kulshreshtha, Tanmai, Dhar, Anindya S.

Journal:

IET Circuits Devices & Systems

Year:

2017

Language:

english

File:

PDF, 4.74 MB

english, 2017

3

Low Latency Pipelined CORDIC-like Rotator Architecture

Boppana, Lakshmi, Dhar, Anindya

Journal:

International Journal of Electronics

Year:

2016

Language:

english

File:

PDF, 501 KB

english, 2016

4

CORDIC-Based High Throughput Sliding DFT Architecture with Reduced Error-Accumulation

Kulshreshtha, Tanmai, Dhar, Anindya Sundar

Journal:

Circuits, Systems, and Signal Processing

Year:

2018

Language:

english

File:

PDF, 4.23 MB

english, 2018

5

A fast VLSI architecture of a hierarchical block matching algorithm for motion estimation

Ghosh, Kausik, Dhar, Anindya Sundar

Journal:

Journal of Real-Time Image Processing

Year:

2016

Language:

english

File:

PDF, 541 KB

english, 2016

6

CORDIC-Based VLSI Architecture for Implementing Kaiser-Bessel Window in Real Time Spectral Analysis

Kailash Chandra Ray, Anindya Sundar Dhar

Journal:

Journal of Signal Processing Systems

Year:

2014

Language:

english

File:

PDF, 525 KB

english, 2014

7

Novel architecture for QAM modulator–demodulator and its generalization to multicarrier modulation

Ayan Banerjee, Anindya S. Dhar

Journal:

Microprocessors and Microsystems

Year:

2005

Language:

english

File:

PDF, 117 KB

english, 2005

8

Pipelined VLSI Architecture using CORDIC for Transform Domain Equalizer

Ayan Banerjee, Anindya Sundar Dhar

Journal:

Journal of Signal Processing Systems

Year:

2013

Language:

english

File:

PDF, 1.00 MB

english, 2013

9

Erratum to: A fast VLSI architecture of a hierarchical block matching algorithm for motion estimation

Ghosh, Kausik, Dhar, Anindya Sundar

Journal:

Journal of Real-Time Image Processing

Year:

2016

File:

PDF, 112 KB

2016

10

[IEEE 2014 IEEE Students' Technology Symposium (TechSym) - Kharagpur (2014.2.28-2014.3.2)] Proceedings of the 2014 IEEE Students' Technology Symposium - Double-fault tolerant architecture design for digital adder

Mukherjee, Atin, Dhar, Anindya Sundar

Year:

2014

Language:

english

File:

PDF, 364 KB

english, 2014

11

Real-time fault-tolerance with hot-standby topology for conditional sum adder

Mukherjee, Atin, Dhar, Anindya Sundar

Journal:

Microelectronics Reliability

Year:

2015

Language:

english

File:

PDF, 896 KB

english, 2015

12

Fault tolerant architecture design using quad-gate-transistor redundancy

Mukherjee, Atin, Dhar, Anindya Sundar

Journal:

IET Circuits Devices & Systems

Year:

2015

Language:

english

File:

PDF, 489 KB

english, 2015

13

High Performance VISI Design of Diamond Search Algorithm for Fast Motion Estimation

Mukherjee, Rohan, Mahajan, Vikrant, Dhar, Anindya Sundar, Chakrabarti, Indrajit

Journal:

Journal of Circuits System and Computers

Year:

2016

Language:

english

File:

PDF, 257 KB

english, 2016

14

High-performance VLSI architectures for M-PSK modems

Mamidala, Chandrakanth, Dhar, Anindya Sundar

Journal:

IET Circuits Devices & Systems

Year:

2017

Language:

english

File:

PDF, 578 KB

english, 2017

15

Fraction phase based low energy frequency calibration: analysis and design

Ghosh, Amitava, Dhar, Anindya S., Halder, Achintya

Journal:

IET Circuits Devices & Systems

Year:

2017

Language:

english

File:

PDF, 3.75 MB

english, 2017

16

CORDIC-Based VLSI Architectures of Running DFT with Refreshing Mechanism

Ray, Kailash Chandra, Dhar, Anindya Sundar

Journal:

Journal of Signal Processing Systems

Year:

2018

Language:

english

File:

PDF, 1.47 MB

english, 2018

17

[IEEE 2018 IEEE International Symposium on Circuits and Systems (ISCAS) - Florence, Italy (2018.5.27-2018.5.30)] 2018 IEEE International Symposium on Circuits and Systems (ISCAS) - A Novel Approach for Fast and Accurate Mean Error Distance Computation in Approximate Adders

Roy, Avishek Sinha, Dhar, Anindya Sundar

Year:

2018

Language:

english

File:

PDF, 595 KB

english, 2018

18

An Improved VLSI Architecture for Triangular Windowed Sliding DFT based on CORDIC Algorithm

Kulshreshtha, Tanmai, Dhar, Anindya

Journal:

IET Circuits Devices & Systems

Year:

2018

Language:

english

File:

PDF, 2.38 MB

english, 2018

19

SIBAM-SIgn Inclusive Broken Array Multiplier Design for Error Tolerant Applications

Roy, Avishek Sinha, Dhar, Anindya Sundar

Journal:

IEEE Transactions on Circuits and Systems II: Express Briefs

Year:

2020

File:

PDF, 576 KB

2020

20

A Novel Paradigm of CORDIC-Based FFT Architecture Framed on the Optimality of High-Radix Computation

Banerjee, Ayan, Dhar, Anindya Sundar

Journal:

Circuits, Systems, and Signal Processing

Year:

2020

File:

PDF, 2.10 MB

2020

21

Architectural design and FPGA implementation of radix-4 CORDIC processor

Kaushik Bhattacharyya, Rakesh Biswas, Anindya Sundar Dhar, Swapna Banerjee

Journal:

Microprocessors and Microsystems

Year:

2010

Language:

english

File:

PDF, 704 KB

english, 2010

22

Adaptive digital phase modulation schemes using transition-initiated phase acceleration

Rajarshi Mahapatra, Anindya Sundar Dhar, Debasish Datta

Journal:

AEU - International Journal of Electronics and Communications

Year:

2008

Language:

english

File:

PDF, 379 KB

english, 2008

23

Integrated voice and data transmission employing adaptive modulation in wireless networks

Rajarshi Mahapatra, Anindya Sundar Dhar, Debasish Datta

Journal:

AEU - International Journal of Electronics and Communications

Year:

2009

Language:

english

File:

PDF, 504 KB

english, 2009

24

An array architecture for computing two-dimensional discrete Hartley transforms

Anindya Sundar Dhar, Swapna Banerjee

Journal:

Computers & Electrical Engineering

Year:

1991

Language:

english

File:

PDF, 398 KB

english, 1991

25

Multiplierless array architecture for computing Discrete Cosine Transform

Manik Chandra Mandal, Anindya Sundar Dhar, Swapna Banerjee

Journal:

Computers & Electrical Engineering

Year:

1995

Language:

english

File:

PDF, 432 KB

english, 1995

26

An array architecture for image reconstruction using the direct Fourier method

Swapnajit Mittra, Anindya S. Dhar, Swapna Banerjee

Journal:

Computers & Electrical Engineering

Year:

1994

Language:

english

File:

PDF, 408 KB

english, 1994

27

A Dimerized Coiled-Coil Domain and an Adjoining Part of Geminin Interact with Two Sites on Cdt1 for Replication Inhibition

Sandeep Saxena, Ping Yuan, Suman Kumar Dhar, Takeshi Senga, David Takeda, Howard Robinson, Sally Kornbluth, Kunchithapadam Swaminathan, Anindya Dutta

Journal:

Year:

2004

Language:

english

File:

PDF, 933 KB

english, 2004

28

Replication from oriP of Epstein-Barr Virus Requires Human ORC and Is Inhibited by Geminin

Suman K. Dhar, Kenichi Yoshida, Yuichi Machida, Poonam Khaira, Biswendu Chaudhuri, James A. Wohlschlegel, Michael Leffak, John Yates, Anindya Dutta

Journal:

Year:

2001

Language:

english

File:

PDF, 594 KB

english, 2001

29

Xenopus Mcm10 Binds to Origins of DNA Replication after Mcm2-7 and Stimulates Origin Binding of Cdc45

James A Wohlschlegel, Suman K Dhar, Tatyana A Prokhorova, Anindya Dutta, Johannes C Walter

Journal:

Year:

2002

Language:

english

File:

PDF, 275 KB

english, 2002

30

[IEEE 2012 Annual IEEE India Conference (INDICON) - Kochi, India (2012.12.7-2012.12.9)] 2012 Annual IEEE India Conference (INDICON) - VLSI architectural design of zoomable real time spectrum analyzer

Sarkar, Sumantra, Dhar, Anindya Sundar

Year:

2012

Language:

english

File:

PDF, 1.12 MB

english, 2012

31

[IEEE 2014 18th International Symposium on VLSI Design and Test (VDAT) - Coimbatore, India (2014.7.16-2014.7.18)] 18th International Symposium on VLSI Design and Test - An ultra low power MICS/ISM band transmitter in 0.18 μm CMOS

Ghosh, Amitava, Dhar, Anindya S., Halder, Achintya

Year:

2014

Language:

english

File:

PDF, 1.77 MB

english, 2014

32

[IEEE 2010 53rd IEEE International Midwest Symposium on Circuits and Systems (MWSCAS) - Seattle, WA, USA (2010.08.1-2010.08.4)] 2010 53rd IEEE International Midwest Symposium on Circuits and Systems - Modified Elmore delay model for VLSI interconnect

Mal, Ashis Kumar, Dhar, Anindya Sundar

Year:

2010

Language:

english

File:

PDF, 422 KB

english, 2010

33

[IEEE 2014 18th International Symposium on VLSI Design and Test (VDAT) - Coimbatore, India (2014.7.16-2014.7.18)] 18th International Symposium on VLSI Design and Test - VLSI design of fast fractal image encoder

Panigrahy, Mamata, Chakrabarti, Indrajit, Dhar, Anindya Sundar

Year:

2014

Language:

english

File:

PDF, 1.39 MB

english, 2014

34

[IEEE TENCON 2009 - 2009 IEEE Region 10 Conference - Singapore (2009.01.23-2009.01.26)] TENCON 2009 - 2009 IEEE Region 10 Conference - VLSI implementation of discrete Mellin transform for real time scale analysis of images

Mazumdar, Amartya, Dhar, Anindya S

Year:

2009

Language:

english

File:

PDF, 618 KB

english, 2009

35

[IEEE APCCAS 2010-2010 IEEE Asia Pacific Conference on Circuits and Systems - Kuala Lumpur, Malaysia (2010.12.6-2010.12.9)] 2010 IEEE Asia Pacific Conference on Circuits and Systems - Design of DXT architecture using current switched integrator

Mal, Ashis Kumar, Hari, Om Prakash, Todani, Rishi, Dhar, Anindya Sundar

Year:

2010

Language:

english

File:

PDF, 354 KB

english, 2010

36

[IEEE 2012 25th International Conference on VLSI Design - Hyderabad, India (2012.01.7-2012.01.11)] 2012 25th International Conference on VLSI Design - Random Access Analog Memory (RA2M) for Video Signal Application

Chattaraj, Nilanjan, Dhar, Anindya Sundar

Year:

2012

Language:

english

File:

PDF, 412 KB

english, 2012

37

[IEEE 2012 International Symposium on Electronic System Design (ISED) - Kolkata, India (2012.12.19-2012.12.22)] 2012 International Symposium on Electronic System Design (ISED) - Design of a Self-Reconfigurable Adder for Fault-Tolerant VLSI Architecture

Mukherjee, Atin, Dhar, Anindya Sundar

Year:

2012

Language:

english

File:

PDF, 367 KB

english, 2012

38

[IEEE 2009 Annual IEEE India Conference - Ahmedabad, India (2009.12.18-2009.12.20)] 2009 Annual IEEE India Conference - VLSI Architecture for Separable Mellin Transform

Mazumdar, Amartya, Dhar, Anindya S.

Year:

2009

Language:

english

File:

PDF, 355 KB

english, 2009

39

SPICE compatible behavioural modelling of resistive sensors

Nandi, Prajit, Sahu, Debashis, Dhar, Anindya Sundar, Das, Soumen

Journal:

Measurement Science and Technology

Year:

2014

Language:

english

File:

PDF, 1.64 MB

english, 2014

40

High Performance VLSI Architecture for Three-Step Search Algorithm

Mukherjee, Rohan, Sheth, Keyur, Dhar, Anindya Sundar, Chakrabarti, Indrajit, Sengupta, Somnath

Journal:

Circuits, Systems, and Signal Processing

Year:

2015

Language:

english

File:

PDF, 1.19 MB

english, 2015

41

Bmi-1: At the crossroads of physiological and pathological biology

Bhattacharya, Resham, Banerjee Mustafi, Soumyajit, Street, Mark, Dey, Anindya, Dwivedi, Shailendra Kumar Dhar

Journal:

Genes & Diseases

Year:

2015

Language:

english

File:

PDF, 855 KB

english, 2015

42

[IEEE 2014 2nd International Conference on Emerging Technology Trends in Electronics, Communication and Networking (ET2ECN) - Surat, India (2014.12.26-2014.12.27)] 2014 2nd International Conference on Emerging Technology Trends in Electronics, Communication and Networking - Parallel architecture for real time computation of discrete Mellin transform

Ray, Kailash Chandra, Dhar, Anindya Sundar

Year:

2014

Language:

english

File:

PDF, 125 KB

english, 2014

43

Inhibition of BMI1 induces autophagy-mediated necroptosis

Dey, Anindya, Mustafi, Soumyajit Banerjee, Saha, Sounik, Kumar Dhar Dwivedi, Shailendra, Mukherjee, Priyabrata, Bhattacharya, Resham

Journal:

Year:

2016

Language:

english

File:

PDF, 1.40 MB

english, 2016

44

[IEEE 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID) - Kolkata, India (2016.1.4-2016.1.8)] 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID) - Efficient Implementation of Scan Register Insertion on Integer Arithmetic Cores for FPGAs

Palchaudhuri, Ayan, Dhar, Anindya Sundar

Year:

2016

Language:

english

File:

PDF, 803 KB

english, 2016

45

Corrigendum to ‘Bmi-1: At the crossroads of physiological and pathological biology’ [Genes & Diseases 2 (2015) 225–239]

Bhattacharya, Resham, Mustafi, Soumyajit Banerjee, Street, Mark, Dey, Anindya, Dwivedi, Shailendra Kumar Dhar

Journal:

Genes & Diseases

Year:

2015

Language:

english

File:

PDF, 254 KB

english, 2015

46

Choice of granularity for reliable circuit design using dynamic reconfiguration

Mukherjee, Atin, Dhar, Anindya Sundar

Journal:

Microelectronics Reliability

Year:

2016

Language:

english

File:

PDF, 2.73 MB

english, 2016

47

[IEEE 2004 IEEE Region 10 Conference TENCON 2004. - Chiang Mai, Thailand (Nov. 21-24, 2004)] 2004 IEEE Region 10 Conference TENCON 2004. - Motion estimation using multi-resolution based on haar wavelet transformation

Sarma, M., Anindya, D.S., Dhar, S.

Year:

2004

Language:

english

File:

PDF, 1.82 MB

english, 2004

48

Research Commentary —Sponsored Search and Market Efficiency

Dhar, Vasant, Ghose, Anindya

Journal:

Information Systems Research

Year:

2010

Language:

english

File:

PDF, 180 KB

english, 2010

49

Effect of single-dose carbapenem exposure on transcriptional expression of blaNDM-1 and mexA in Pseudomonas aeruginosa

Choudhury, Debarati, Paul, Deepjyoti, Ghosh, Anindya Sundar, Das Talukdar, Anupam, Dutta Choudhury, Manabendra, Maurya, Anand Prakash, Dhar (Chanda), Debadatta, Chakravarty, Atanu, Bhattacharjee, Amit

Journal:

Journal of Global Antimicrobial Resistance

Year:

2016

Language:

english

File:

PDF, 346 KB

english, 2016

50

[IEEE 2016 Twenty Second National Conference on Communication (NCC) - Guwahati, India (2016.3.4-2016.3.6)] 2016 Twenty Second National Conference on Communication (NCC) - Hardware implementation of quadtree based fractal image decoder

Panigrahy, Mamata, Chakrabarti, Indrajit, Dhar, Anindya Sundar

Year:

2016

Language:

english

File:

PDF, 439 KB

english, 2016

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